1. Field of the Invention
The present invention relates to multi-stage pipelined analog to digital converters in which each stage includes a bit-and-one-half analog to digital sub-converter, and particularly relates to reductions in differential non-linearities for such an analog to digital converter.
2. Background of the Invention
Multi-stage pipelined analog to digital converters (ADC) provide efficient high speed conversion of analog signals to digital equivalents A representative multi-stage pipelined ADC 10 is shown in FIG. 1. As seen there, ADC 10 includes multiple stages such as stages 11, 12 and 13 each providing one or more bits of digital data to a digital correction circuit 15, which resolves the digital outputs from each stage into an overall digital output 16 that corresponds to an analog input 17. Each stage is a switched capacitor circuit operating in response to clock signals such as "PHgr"1 and "PHgr"2 and comparing an analog voltage input to thresholds based on reference signals Vrefp and Vrefn so as to produce the digital outputs as well as a residual analog signal. The residual analog signal is provided as input to the subsequent stage.
FIG. 2 is a generalized block diagram of each stage. As seen in FIG. 2, each stage applies its input analog voltage to a multiplying digital to analog converter (MDAC) 19 so as to generate its residual output analog voltage. This output voltage is provided to comparator 18 which generates the digital output. MDAC 19 uses this digital output, together with clock signal "PHgr"1 and "PHgr"2 and reference voltages Vrefp and Vrefn, to generate the residual output analog voltage.
FIG. 3A illustrates a typical MDAC 19. As seen there, during sample phase "PHgr"1, an input voltage signal is sampled and stored on capacitors C1 and C2. During amplification phase "PHgr"2, capacitor C1 is placed in the feedback leg of amplifier 21, and a voltage is applied to capacitor C2 in accordance with whether the digital output from comparator 18 is a digital 1 or a digital 0. As a consequence of this arrangement, so long as capacitors C1 and C2 are exactly equal, the output from MDAC 19 is a correctly multiplied residual voltage in dependence on the digital data generated at a stage, as shown in FIG. 3B.
Most often, however, capacitors C1 and C2 are not equal, resulting in a non-ideal slope for the digital converter, as shown in FIG. 3C. The non-ideal slope results in missing codes or wide codes. In FIG. 3C, it is assumed that C1 is slightly smaller than C2. Thus, the drop from voltage Va to Vb is slightly less than one digital bit, resulting in wide codes as shown in FIG. 3D. Of course, if C2 greater than C1, then Vaxe2x88x92Vb greater than one digital bit, resulting in unillustrated missing codes.
One solution to capacitor mismatch has been proposed by Yu, et al., xe2x80x9cA 2.5-V, 12-b, 5-Msample/s Pipelined CMOS ADCxe2x80x9d, IEEE Journal of Solid State Circuits, Vol. 31, No. 12, p. 1854 (Dec. 1996). Yu, et al. proposed a commutated feedback-capacitor switching technique in which the role of the feedback capacitor is switched in dependence on the digital data. With the Yu, et al. technique, differential non-linearity is reduced, as seen in FIG. 3E, since the voltage drop Vaxe2x88x92Vb is very nearly equal to one digital bit. Thus, wide codes and missing codes are avoided, and differential non-linearity is reduced as shown in FIG. 3F.
Another difficulty encountered with the multi-stage pipelined ADC shown in FIG. 1 is the problem caused by an undesired offset in comparator 18. As shown in FIG. 4A, with an undesired or uncompensated offset in comparator 18, missing codes are encountered because of a shift in the transfer function of MDAC 19. One solution proposed for this difficulty is the provision of multiple bits from each stage as already described. The bits are generated by comparison with thresholds which are +/xe2x88x92xc2xc of the comparison range centered symmetrically around zero. With multiple bits for each stage, a transfer function such as in FIG. 4B is obtained, in which two bits of digital output are obtained for each stage, and the digital outputs of all stages are resolved by correction circuitry 15 so as to result in the overall ADC output. The arrangement shown in FIG. 4D is often referred to as a xe2x80x9cbit-and-one-half converterxe2x80x9d.
Combining the techniques of bit-and-one-half converters with the Yu, et al. technique of commutated feedback-capacitor switching is expected to yield a highly efficient pipelined ADC with good differential non-linearity. However, one source of differential non-linearity remains, as follows.
Specifically, commutated feedback-capacitor switching works in single-bit MDACs because the voltage drop from the voltage Va to Vb is approximately equal to one bit. However, in bit-and-a-half MDACs, when capacitive mismatch is present, the voltage drop from Va to Vb is not equal to one bit as seen in FIG. 5A, resulting in differential non-linearity shown in FIG. 5B. Thus, commutated feedback-capacitor switching in bit-and-a-half MDACs only reduces differential non-linearity by about 50%, primarily because of unequal threshold spacing between the 00 and 01 decision point and between the 01 and 11 decision point.
It is an object of the present invention to reduce differential non-linearity in bit-and-one-half analog to digital converter by threshold-stretching the threshold at which each stage of the bit-and-one-half converter operates.
In more detail, FIG. 6A is a graph showing input versus output for one stage of a multi-stage bit-and-one-half ADC. As seen there, the threshold for conversion has been shifted outwardly relative to the threshold shown in the conventional arrangement of FIG. 5A. As a result, the voltage drop from Va to Vb is much closer to the desired one bit at which commutated feedback-capacitive switching operates most ideally, yielding an overall transfer curve shown in FIG. 6B in which differential non-linearity, though still present, is reduced relative to the conventional arrangement shown in FIG. 5B.
Thus, in one aspect the invention is a bit-and-one-half conversion stage for a multi-stage pipelined ADC in which conversion thresholds are stretched outwardly relatively to corresponding thresholds in conventional conversion stages. Shifting outwardly too much completely destroys the effectiveness of bit-and-one-half conversion such that when the thresholds are shifted completely to the edge of positive and negative reference voltages divided by two (i.e., Vrefn/2 and Vrefp/2), the benefits of bit-and-one-half conversion are eliminated. An intermediate shift is therefore preferable; the inventor herein has determined that for a 1% mismatch in capacitance, a preferred shift is a shift outwardly of approximately 0.125 (normalized to +1 and xe2x88x921 reference voltages) from conventional threshold locations of +/xe2x88x92xc2xc.
Also, with reference to FIG. 6A, by shifting the positive threshold to the right by approximately Vrefp/8, and by shifting the negative threshold to the left by approximately Vrefn/8, a desired drop in residue can be achieved. The entire residue is preferably located inside the window (e.g., the box) shown in FIG. 6A. However, when using the entire capability of error correction logic to compensate for capacitor mismatch, op-amp and comparator offset (plus charge injection) may cause differential non-linearity noise.
The shift in threshold can be obtained by a variety of techniques, including simple resistive ladders, internal generation of reference voltages, or converter-wide reliance on globally-generated thresholds.
In another aspect, the invention is a multistage pipelined ADC using the aforementioned bit-and-one-half converter with outwardly stretched conversion thresholds.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiment thereof in connection with the attached drawings.